Field of the Invention
The present invention relates to a signal processing apparatus and signal processing method, and image capturing apparatus, and particularly relates to a signal processing apparatus and signal processing method, and image capturing apparatus that perform analog-digital conversion.
Description of the Related Art
Recently, a common television standard has been changed from a television standard called “full high-definition”, in which there are 1,920 horizontal pixels and 1,080 vertical pixels, to a television standard called “4K2K”, in which there are 3,840 horizontal pixels and 2,160 vertical pixels, that are four times as much as pixels in a television standard called “high-definition”. Further transitions to a next-generation television standard called “8K4K” (“ultra-high-definition”), in which there are 7,680 horizontal pixels and 4,320 vertical pixels, are expected in the future. As the number of pixels increases, framerates continue to increase as well.
The transition to such television standards has resulted in increased demand for more pixels and higher framerates in image capturing apparatuses that shoot video for television, and increasing the speed at which an image sensor for converting light into an electric signal reads out such video is an issue with respect to meeting such demand. To increase the readout speed, it is absolutely necessary to increase the processing speed of an AD converter provided in the image sensor.
On the other hand, in order to record a high-quality video, there is a demand for a higher number of bits of a video signal. However, in order to perform AD conversion with a high number of bits, the time required for AD conversion increases. Japanese Patent Laid-Open No. 2013-236362 discloses a technique in which an AD conversion is performed on a signal of a low level after amplifying the signal with a gain, a normal AD conversion is performed on a signal of a high level, and the levels of the AD-converted signals are corrected so as to compensate for the difference by the gain. In this manner, the number of bits is increased without increasing the time required for performing AD conversion.
However, in the above conventional example, there are cases where the correction error becomes an issue when correction is performed on signals that were AD-converted with different gains using a ramp signal and so forth. For example, in a case where noise or non-linear characteristics arise in an AD conversion circuit, the correction error becomes more conspicuous. Further, in a case where there are a plurality of changing points of gains, the correction error may become large depending on a changing point.